Discussion:
R820T Tuning Range - revisited
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Dennis Sheirer
2014-09-26 15:36:59 UTC
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Dennis Sheirer
2014-09-26 15:41:17 UTC
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(reposting as plain text)

I've been experimenting with the tuning range of the R820T tuner. I found that I can reliably set the center tuned frequency of the R820T across the entire range of 3.18 MHz to 1782.03 MHz with successful PLL lock for all frequencies in that range.

Although the tuner can be set to that range, it still appears deaf to anything below ~ 24 MHz on the lower end. I don't have a signal generator to test the full range, nor have I yet experimented with changing any of the other registers, filters or IF settings while tuned in the lower frequency range.

Here are the frequency divider, integral and sigma-delta modulator register settings/formulas to support tuning the full frequency range:

Frequency Divider (read: Divider, Min Frequency, Max Frequency, Register Setting, Integral Size( 1/32 of max - min)
DIVIDER_0, 864000000, 1785600000, 0x00, 28800000 ),
DIVIDER_1, 432000000, 892800000, 0x20, 14400000 ),
DIVIDER_2, 216000000, 460800000, 0x40, 7200000 ),
DIVIDER_3, 108000000, 223200000, 0x60, 3600000 ),
DIVIDER_4, 54000000, 111600000, 0x80, 1800000 ),
DIVIDER_5, 27000000, 55800000, 0xA0, 900000 ),
DIVIDER_6, 13500000, 27900000, 0xC0, 450000 ),
DIVIDER_7, 6750000, 13950000, 0xE0, 225000 );

Integral (PLL) = 32 integral units of the divider's frequency span (read: number, register setting)
I00( 0, 0x44 ),
I01( 1, 0x84 ),
I02( 2, 0xC4 ),
I03( 3, 0x05 ),
I04( 4, 0x45 ),
I05( 5, 0x85 ),
I06( 6, 0xC5 ),
I07( 7, 0x06 ),
I08( 8, 0x46 ),
I09( 9, 0x86 ),
I10( 10, 0xC6 ),
I11( 11, 0x07 ),
I12( 12, 0x47 ),
I13( 13, 0x87 ),
I14( 14, 0xC7 ),
I15( 15, 0x08 ),
I16( 16, 0x48 ),
I17( 17, 0x88 ),
I18( 18, 0xC8 ),
I19( 19, 0x09 ),
I20( 20, 0x49 ),
I21( 21, 0x89 ),
I22( 22, 0xC9 ),
I23( 23, 0x0A ),
I24( 24, 0x4A ),
I25( 25, 0x8A ),
I26( 26, 0xCA ),
I27( 27, 0x0B ),
I28( 28, 0x4B ),
I29( 29, 0x8B ),
I30( 30, 0xCB ),
I31( 31, 0x0C );

Sigma Delta Modulator - residual frequency remaining after divider and integral settings

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Formula - example of setting 452.345000 MHz:

1) Add the IF frequency to the target frequency

452,345,000 + 3,570,000 = 455,915,000

2) Select the lowest numbered frequency divider that contains the frequency (min < freq < max )

Divider = 1 (Register 0x10 setting: 0x20)

2) Subtract the divider minimum frequency from the target frequency, then divide by the integral size to get the integral setting.

455,915,000 - 432,000,000 = 23,915,000

23,915,000 / 14,400,000 = 1 (PLL Register 0x14 setting: 0x84 );

3) Divide the remaining frequency residual by the integral size and left-shift 16 bits to get the SDM register settings

23,915,000 - ( 14,400,000 * 1 ) = 9,515,000

9,515,000 / 14,400,000 = 0.6607638888888889

0.6607638888888889 << 16 = 0xA927 (SDM Register 0x16 setting: 0xA9, SDM Register 0x15: 0x27 )

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With an IF setting of 3.57 MHz, below are the actual tuning ranges for each of the frequency dividers:

Divider 0: 860.43 to 1782.03 MHz
Divider 1: 428.43 to 889.23 MHz
Divider 2: 212.43 to 457.23 MHz
Divider 3: 104.43 to 219.63 MHz
Divider 4: 50.43 to 108.03 MHz
Divider 5: 23.43 to 52.23 MHz
Divider 6: 9.93 to 24.33 MHz
Divider 7: 3.18 to 10.38 MHz

I haven't yet experimented with the 4.57 MHz IF setting, but that would push the low end tunable frequency down to 2.18 MHz.

A working java example of this formula is here (see: setPLL() method ):

https://code.google.com/p/sdrtrunk/source/browse/trunk/src/source/tuner/rtl/r820t/R820TTunerController.java

Denny
Oliver Jowett
2014-09-26 16:27:09 UTC
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Post by Dennis Sheirer
Although the tuner can be set to that range, it still appears deaf to anything below ~ 24 MHz on the lower end. I don't have a signal generator to test the full range, nor have I yet experimented with changing any of the other registers, filters or IF settings while tuned in the lower frequency range.
My experience is that divider values of 6/7 (= divide-by-128 or
divide-by-256) seem to just throw away the PLL output entirely.
That divider doesn't affect PLL operation, so you'll still get PLL
lock, but I never got any useful signal anywhere across the 14MHz
visible to the 2832 with those divider values.

Oliver

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